CV

Education

• Ph.D in Computer Engineering, University of Central Florida, 2021
• M.S. in Electrical Engineering, University of Central Florida, 2017
• B.S. in Electrical and Electronics Engineering, University of Gaziantep, 2013

Work experience

• 01/2022 - Present: Lead Software Engineer at Cadence Design Systems
• 05/2021 - 09/2021: Intern Software Engineer at Cadence Design Systems
• 01/2017 - 12/2021: Research and Teaching Assistant at University of Central Florida
• 07/2013 - 07/2014: R&D - Embedded Systems Engineering at EuroTechLab (Euroquipments)

Skills

• Programming Languages
  • C, C++
  • Embedded C
  • Python
• Softwares & Tools & Scripting
  • Matlab
  • IBM Cplex
  • Cadence Virtuoso
  • HSpice, Ngspice scripting
  • bash, tcl scripting

Research Interest

• Electronic Design Automation
• Physical Design of VLSI
• Computer Aided Design for Emerging Technologies

Publications

Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew

Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current

Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew

N. Uysal and R. Ewetz, "An OCV-Aware Clock Tree Synthesis Methodology," 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Munich, Germany, 2021, pp. 1-9, doi: 10.1109/ICCAD51958.2021.9643585.

Teaching

Full-custom VLSI Design (Lab Assistant)

Embedded Systems (Lab Instructor)

Computer Organization

Services and Memberships

• IEEE Grad Student Member