Necati Uysal

Necati Uysal

Lead Software Engineer, Ph.D.

Publications

Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew

Published in 2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2021

In this paper, we propose an OCV-aware clock tree synthesis methodology that aims to rethink how to account for OCVs. The key idea is to predict the impact of OCVs early in the synthesis process, which allows the variations to be compensated for using non-uniform safety margins. This results in a synthesis flow that is almost correct-by-design.

Recommended citation: N. Uysal and R. Ewetz, "An OCV-Aware Clock Tree Synthesis Methodology," 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Munich, Germany, 2021, pp. 1-9, doi: 10.1109/ICCAD51958.2021.9643585. https://par.nsf.gov/servlets/purl/10351582#:~:text=The%20proposed%20OCV-aware%20clock,variations%20within%20every%20timing%20constraint.

Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current

Published in International Symposium on Physical Design, 2020

Circuits deployed in the Internet of Things operate in low and high performance modes to cater to variable frequency and power requirements. Consequently, the clock networks for such circuits must be synthesized meeting drastically different timing constraints under variations in the different modes. The overall power consumption and robustness to variations of a clock network is determined by the topology. However, state-of-the-art clock networks use the same topology in every mode, despite that the timing constraints in the low and high performance modes are very different. In this paper, we propose a clock network with a mode reconfigurable topology (MRT) for circuits with positive-edge triggered sequential elements. In high performance modes, the required robustness to variations is provided by reconfiguring the MRT structure into a near-tree. In low performance modes, the MRT structure is reconfigured into a tree to save power. Non-tree (or near-tree) structures provide robustness to variations by appropriately constructing multiple alternative paths from the clock source to the clock sinks, which neutralizes the negative impact of variations. In MRT structures, OR-gates are used to join multiple alternative paths into a single path. Consequently, the MRT structures consume no short circuit power because there is only one gate driving each net. Moreover, it is straightforward to reconfigure MRT structures into a tree by gating the clock signal in part of the structure.

Recommended citation: https://dl.acm.org/doi/abs/10.1145/3372780.3375559